SCHEME OF EXAMINATION for Master of Science in ASIC DESIGN
Paper
NAME OF THE SUBJECT
DURATION OF EXAM IN HOURS
MARKS FOR
IA
EXAM
TOTAL
Paper 1
BASIC VLSI & ANALOG DESIGN
3
20
80
100
Paper 2
ASIC DESIGN
Paper 3
CAD TOOL FOR VLSI
Paper 4
ELECTIVE I
Paper 5
ELECTIVE II
Total:
15
400
500
1.DIGITAL CIRCUIT DESIGN USING VERILOG
1. PLD AND FPGA
2. RF MICRO ELECTRONIC CHIP DESIGN
2. LOW POWER VLSI DESIGN
FINAL
Paper 6
VLSI TECHNOLOGY & SYSTEM ON CHIP
Paper 7
ELECTIVE III
Paper 8
PROJECT WORK
THESIS EVAL. &
VIVA VOCE
-
300
140
560
700
VLSI and DSP-Driven Computer Systems
Nanoelectronics
GRAND TOTAL: PREVIOUS + FINAL = 1200 Download Scheme and Syllabus